The present invention relates generally to logic arrays and, more specifically, to a method of testing logic arrays including programmable type logic arrays.
A logical array in its more generic term is considered to have an logical AND matrix and a logical OR matrix. As is illustrated in FIG. 1, the inputs I.sub.O through I.sub.M are provided to input buffers 14 which provide true and complementary inputs into a logical AND matrix 12. The output of the logical AND matrix 12 at line 16 are provided as inputs to the logic OR matrix 18. The output of the logical matrix 18 are provided throughout the buffers 20 as outputs 0.sub.O through 0.sub.N.
The most versatile logic array is known as the Programmable Logic Array (PLA). The PLA has a programmable logical AND matrix and a programmable logic OR matrix. The AND matrix produces the product terms whereas the OR matrix produces the summing terms. Thus, by programming the logical AND matrix and the logical OR matrix, specific logical equations or functions can be performed as the sum of products. It should be noted that the logical AND and the logic OR matrix are used as generic terms and may be performed in negative logic versus positive logic. Similar logical equations can be produced by PLAs as the products of sums or the inverse of product of sums. The advantage of PLAs is that by providing a programmable logical AND matrix you can create only the necessary product terms from less than all the inputs and provide an input ot the logical OR matrix. Since fewer product terms are required, the size of the logical AND matrix is reduced.
A variation of the PLA is the Programmable Read Only Memory (PROM). The PROM uses a non-programmable logical AND matrix and a programmable OR matrix. The AND matrix in a PROM provides a unique single output 16 as an input to the logical or matrix 18 as a function of all the inputs I.sub.O through I.sub.M and, thus, is a full decoder. It is distinguishable from the PLA wherein any or all of the inputs I.sub.O through I.sub.M are used to produce one or more outputs 16 from the AND matrix 12.
Another variation on the PLA is known as a Programmable Array Logic (PAL). The PAL includes a programmable logic AND matrix and a non-programmable OR matrix. To further reduce the size of the non-programmable OR matrix, some PALs have the output of the AND matrix 16 connected to selected, prededicated OR gates.
The testing of PLAs and PALs has generally been a D.C. test or tests of the specific connections of the AND and OR matrix. Special row and column decoders have been provided for the AND and OR matrix to isolate each location in the matrix by row and column. This is needed since the input buffers may be connected to more than one column and more than one output may be produced from the AND matrix. Although this type of testing verifies the AND and OR logical matrices, they do not provide an A.C. test of the input and output circuitry. It is not a serious problem for the PROMs since for a specific combination of inputs to the AND matrix there is only one input from the AND matrix to the OR matrix. But even for this type of test, a failure during the A.C. testing of the input and output circuitry may be the result of a defect in the AND or OR matrix and, thus, it cannot be isolated to the input or output circuitry.
If the input and output circuitry were to be tested, it would have to be probe tested prior to packaging. Thus, the final packaged device would not be tested in various environments, nor could the programmed device, except for the AND and OR matrix as previously described.
Thus, there exists the need for a method and apparatus of testing logic arrays which will test the input and output circuitry independent of the AND and OR matrices.